| PART |
Description |
Maker |
| 2020-900 2020-1400 2021-200 2021-250 2020-700 2021 |
Delay 900 /-18 ns, fixed SIP delay line Tr
Delay 1400 /-28 ns, fixed SIP delay line Tr
Delay 200 /-10 ns, fixed SIP delay line Tr
Delay 250 /-10 ns, fixed SIP delay line Tr
Delay 700 /-14 ns, fixed SIP delay line Tr
Delay 100 /-10 ns, fixed SIP delay line Tr
Delay 150 /-10 ns, fixed SIP delay line Tr
Delay 500 /-10 ns, fixed SIP delay line Tr
Delay 1300 /-26 ns, fixed SIP delay line Tr
|
Data Delay Devices Inc
|
| CY28343 CY28343OC CY28343OCT |
Zero Delay SDR/DDR Clock Buffer
|
CYPRESS[Cypress Semiconductor]
|
| ICS93705 ICS93705YF-T |
DDR Phase Lock Loop Zero Delay Clock Buffer
|
Integrated Circuit Systems
|
| ICS93776 |
Low Cost DDR Phase Lock Loop Zero Delay Buffer
|
Integrated Circuit Systems
|
| 1507 1507-100A 1507-100B 1507-100C 1507-150A 1507- |
Delay 50 /-2.5 ns, 10-TAP SIP delay line Td/Tr=5
Delay 300 /-15 ns, 10-TAP SIP delay line Td/Tr=5
Delay 200 /-10 ns, 10-TAP SIP delay line Td/Tr=5
Delay 250 /-13 ns, 10-TAP SIP delay line Td/Tr=5
Delay 150 /-7.5 ns, 10-TAP SIP delay line Td/Tr=5
Delay 100 /-5 ns, 10-TAP SIP delay line Td/Tr=5
Ultra-Low-Power Voltage Detectors and µP Supervisory Circuits 固定10抽头延迟线被动园
Ultra-Low-Power Voltage Detectors and µP Supervisory Circuits
Delay 40 /-2 ns, 10-TAP SIP delay line Td/Tr=5
Delay 500 /-25 ns, 10-TAP SIP delay line Td/Tr=5
Delay 20 /-2 ns, 10-TAP SIP delay line Td/Tr=5
|
Data Delay Devices Inc
|
| TC670ECHTR TC67003 TC670 |
The TC670 is an integrated fan speed sensor that predicts and/or detects fan failure, preventing thermal damage to systems with cooling fans. When the fan speed falls below a user specified level, the TC670 asserts an ALERT signal. With th
Tiny Predictive Fan Failure Detector
|
Microchip Technology
|
| TC647BEUATR TC642B TC642BEOA713 TC642BEOATR TC642B |
PWM Fan Speed Controllers With Minimum Fan Speed, Fan Restart and FanSense⑩ Technology for Fault Detection
|
MICROCHIP[Microchip Technology]
|
| 3D7010SERIES 3D7010S-80 3D7010S-90 3D7010S-400 |
300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit 整体0 - TAP在固定延迟线
MONOLITHIC 10-TAP FIXED DELAY LINE
Delay 8 /-1.5 ns, monolithic 10-TAP fixed delay line
Delay 9 /-1.7 ns, monolithic 10-TAP fixed delay line
Delay 40 /-4 ns, monolithic 10-TAP fixed delay line
|
Interpower, Corp.
Data Delay Devices Inc
|
| IDT72T40108L6-7BB IDT72T40118L6-7BB IDT72T40118L6- |
64K x 40 TeraSync DDR FIFO, 2.5V
128K x 40 TeraSync DDR FIFO, 2.5V
2.5 VOLT HIGH-SPEED TeraSync?? DDR/SDR FIFO 40-BIT CONFIGURATION
16K x 40 TeraSync DDR FIFO, 2.5V
32K x 40 TeraSync DDR FIFO, 2.5V
|
IDT
|
| HY5DU561622DTP HY5DU561622DLTP HY5DU561622DLTP-K H |
DDR SDRAM - 256Mb
256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
|
HYNIX[Hynix Semiconductor]
|
